红绿灯路口

AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明(AD7760 Full Function Support with Additional Instructions)

出租车模块设计加nios2设计cup程序代码 出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code

基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules

说明：  该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

VHDL语言基本数学运算库-VHDL basic arithmetic library

本文件是周立功试验开发板的配套资料，容易学会-This document is ZLG test development board supporting information, easy to learn

从入门到精通，从简单到难，带你轻轻松松玩转FPGA(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)

时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)

用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time

8通道同步AD芯片7608的FPGA控制程序(FPGA control program of ad7608(8 channel synchronous AD chip))