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基于FPGA的数字频率计VHDL源码(精确到1.1hz至20.0mhz)
当时是用于课程设计而编写的代码,经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码(精确到1.1hz至20.0mhz)
- 2022-02-14 20:48:42下载
- 积分:1
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or1200.tar
OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
- 2014-12-20 04:40:23下载
- 积分:1
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ahb_verilog_design
代码为ahb interface ,用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)
- 2020-12-21 14:49:07下载
- 积分:1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言,支持VHDL和verilog 语言方便移植,如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分:1
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TCM解码,VHDL代码,是我在工作中做的工程代码,时序稳定,里面有syn以及软判决的算法,经典...
TCM解码,VHDL代码,是我在工作中做的工程代码,时序稳定,里面有syn以及软判决的算法,经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
- 2022-09-27 21:25:03下载
- 积分:1
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add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)
- 2009-07-20 08:18:37下载
- 积分:1
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verilog基础练习,介绍怎样编写测试文件和仿真
verilog基础练习,介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation
- 2022-01-28 18:39:08下载
- 积分:1
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pps_ketiao_rb2
FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1
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Altera in the official line on the SOPC custom component (PWM) of the examples a...
Altera官网上关于SOPC中自定义组件(PWM)的实例,官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
- 2022-02-04 13:32:48下载
- 积分:1
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shi01
FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)
- 2017-10-24 16:41:14下载
- 积分:1