用于当前电子的开关电源转换器（开关电源）。

一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller" s 8 Design and Implementation

一种压缩感知信号恢复算法，针对贪婪迭代类算法中的正交匹配追踪（OMP)算法的改进。OMP在每次迭代过程中选择出的原子并不是最优的，无法使本轮迭代中残差的减少最大化。本例程实现了改进的最优OMP算法，即Optimised_OMP，保证每次迭代选出的原子与已选出的原子序列所构成的平面正交，因而可以使残差下降的更快，从而加速算法收敛。(A compressed sensing signal recovery algorithms track (OMP) algorithm and orthogonal matching algorithm greedy iterative class. The OMP selected atoms in each iteration of the process is not optimal, not be able to maximize the reduction of the residual in the current round of iteration. The routines to achieve the optimal OMP algorithm improvements that Optimised_OMP, to ensure that each iteration selected atoms with atomic sequence elected a plane orthogonal, and thus can make the residuals have declined even faster, thus speeding up the algorithm convergence.)

至于FSK调制原理就不多说了，这里做的一个实验是二进制频移键控。发送一组码元，通过响应的键控电路监测是发1还是发0然后选择频率控制正余弦电路波形。-see

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

RobustVerilog生成verilog工具(RobustVerilog version)

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

电子时钟VHDL程序与仿真的vhdl源代码-Electronic clock and simulation of VHDL procedures vhdl source code

说明：  QSPI_FLASH_MODEL 可以设计时前端仿真使用(QSPI?_Flash_Model can be used in front-end simulation at design time)