Sequence Detection VHDL source code, ATERA platform compile. Report detailed des...

vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统

FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.

Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)

用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)

PCIe demo sample code

VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈-vidicon s catch and collection in VHDL

uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device

表决器，简单实现了表决功能，无显示功能 -vote

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

这是1C6开发板上元件的具体资料。此开发板有掉电不丢失程序的功能，就是靠着几个芯片(development board components specific information. This development board is not lost restart procedures, it was relying on a few chips)