表决器，简单实现了表决功能，无显示功能

VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2

异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)

可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)

基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码 (DPLL)

ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

基于FPGA的2FSK调制解调，里面有详细的工程说明，对于学习ISE软件和通信原理的知识很有帮助(FPGA based 2FSK modulation and demodulation, which contains detailed engineering instructions, for learning ISE software and communication principles of knowledge is very helpful.)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

1、 利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、 利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、 输出波形要求： 在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz； 在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、 通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.

Xilinx PicoBlaze application developed in ISE10.1.3.

ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)