FM radio decoder and controller VHDL, Xilinx provide. I thank other.

pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

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用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

对ad0809的控制代码( ad0809control)

说明：  mojo v3 complete eagle schematic

详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)

alu 模块，算术逻辑单元，实现简单的控制模块，有最基本的几条指令-alu instruction

数控分频器的设计 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)

说明：  FPGA和双端口RAM的DDS任意波形发生器的实现(FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator)