基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。...

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read

高科技的发展使芯片设计不再是半导体工业的领域，现场可编程逻辑阵列（FPGA）的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专院校学生，使您能够在最短的时间内掌握FPGA的应用与VHDL/AHDL/Verilog HDL这一电子逻辑设计利器，迅速的加入高级电子设计人才行列。-The development of high-tech chip design is no longer the field of semiconductor industry, field programmable logic arrays (FPGA) through the emergence of chip design software to quickly achieve the possible. This system is a broad global engineering and technical personnel and college students, so that you can in the shortest possible period of time to master the application of FPGA and VHDL/AHDL/Verilog HDL logic design of the electronic weapon, quickly adding advanced electronic design talent ranks.

说明：  Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。-FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)