基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。...

文章论述如何将向modelsim中添加仿真库，包括添加xilinx,altera,actel公司的仿真库的方法-Article on how to add ModelSim simulation library, including the add xilinx, altera, actel the company

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)

串行数据开发实用代码， 适合初级学习者使用 很不错(Serial data to develop a practical code for primary learners use very good)

四位除法器的VHDL源程序-four division of VHDL source

Efficient CIC filter Implementation using VHDL

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd

说明：  将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)

自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,

Verilog语言下QAM调制的DDS实现(The QAM Modulation DDS achieve)

quartus一个完整的设计例子,从安装到实例完成，仿真等全过程，适合从0开始的初学者-Quartus a complete design examples, examples from installation to completion, the entire process of simulation, etc., suitable for the beginner to start from 0