SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块...

The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. This contribution attempts to provide a state-of-the-art description of this topic. First, the advantages of reconfigurable hardware for cryptographic applications are discussed from a systems perspective. Second, potential security problems of FPGAs are described in detail, followed by a proposal of a some countermeasure. Third, a list of open research problems is provided. Even though there have been many contributions dealing with the algorithmic aspects of cryptographic schemes implemented on FPGAs, this contribution appears to be the first comprehensive treatment of system and security aspects.

说明：  这个事VHDL基础知识，内面主要内容是编码器的插V过程，值得下载学习！(it is really useful for those who never touch it!)

Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.

5分代码及说明，verilog代码，几乎所有的IC面试都会问到这个问题，所以总结了一下发了上来，共同学习！-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!

stc12c5a60s2单片机做的两路呼吸灯，可以用ad和按键控制闪动频率(stc12c5a60s2 SCM done with the two breathing lights, you can use the ad and buttons to control the flashing frequency)

这是一个VHDL项目，用于在VIRTEX-4 xc4vsx35 FPGA板中执行接收信号的14位ADC。

接口键盘和液晶屏上AT89S52代码

本文描述了fpga中的亚稳态时如何产生的，以及如何计算亚稳态的平均无故障时间。对了解亚稳态有帮助。-This paper describes the sub-fpga how the steady state, as well as how to calculate the metastable MTBF. The understanding of metastable helpful.

进阶实验之SRAM测试，由verilog编写，可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)

说明：  FPGA——IP_RAM实验： 创建IPRAM核，单端口，10位地址线（256字节），8位数据线（每字节8byte），读写使能 input [9:0] address; input clock; input [7:0] data; input wren; //置1则写入 output [7:0] q; LNXmode：控制LEDC显示 1：mode1，从k1~k3输入data的低4位，ledb计时，从0~f，计时跳变沿读取k1~k3的值，存入RAM 8个数之后，从RAM输出数据，用leda显示，同样每秒变化一次(The experiment of FPGA-IP_RAM: Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)