UART VHDL Quartus

PWM整流器的死区延迟的VHDL编程，可以参考一下(VHDL programming PWM Rectifier dead-band delays)

简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform. Please configure it according to the test environment before download and implement the program to FPGA)

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。(Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.)

lattice的串口仿真的程序- serial port simulated programme of lattice

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

FPGA的测频程序，用了D触发器，能测1hz到几百hz(FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz)

Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)

《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7

Altium Reference design for LMH0340 test bed and design