UART VHDL Quartus

用VERILOG语言实现的通用异步串行收发器（RS232收发器），波特率可设置，通讯稳定，已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)

单片机4路ad模数转换数码管动态显示程序(4-way ad microcontroller analog to digital conversion digital tube dynamic display program)

SOC Verfication Methodology and Techniques

网上分享的一段100例子，适合FPGA学习的初学者。内部还有一些经典实用技巧。                                                                        

说明：  一维超混沌随机数的生成verilg，还有testbench仿真激励，modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)

About 1588 PTP protocol xillinx FPGA running code and Software application, and to introduce documents, want to help everyone

11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated

vhdl code for alu and detemines the basic components of alu unit in cpu system

vga，显示彩条，及其简单易懂，适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)