不错的介绍verilog的电子文档，对于入门级的新手有不错的参考价值...

电梯控制 记忆，上升下降停站 超载报警故障.....。-Verilog EDA dianti

example of BCH and RS codecs

自己写的FPGA实现电子琴的VHDL程序，曲目是两只老虎，用到一些模块，和片内存储间，呵呵(FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh)

SDIO Verilog Sourcw code

实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)

8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 (verilog of 8bit error checkout )

This Book description about LCD in Board DE2

说明：  Matlab to hdl code for Least_square testbench

此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )