VHDL 与数字电路设计程序参考书所有程序 1

交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss

本文详细介绍了我们的电气工程项目；

VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )

EGO1快速上手指南，适用于新手进行学习(EGO1 Quick Start Guide)

crc5 bolck in usb contreoller

DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways

Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1

说明：  文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)