16个VHDL 编程实例

上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)

超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載(Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download)

十进制精确计数，经典写法，便于学习与参考，供大家分享-Decimal precision counts, classic written, easy learning and reference for all to share

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

单相数字锁相环 鉴相器 环路滤波器 数控振荡器(Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator)

一个VEILOG HDL程序，可以直接应用，-A VEILOG HDL procedures, can be applied directly,

VHDL、Verilog HDL语言，是华为公司的技术指导书，希望对你有所帮助-VHDL、Verilog HDL

LDPC码的FPGA实现，大家相互学习下。。(the code of LDPC implementation by FPGA)

vhdl adder with two input 4-bit and output of 4 bits and carry

用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)