maxplus2为开发环境 vhdl编写的自由 计数器 程序

VHDL programmes for basic digital circuits. begineers can learn easily

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。

VHDL code for 32 byte RAM

verilog hdl verilog hdl verilog hdl-verilog hdl

xapp from xilinx very hard to find and very usefull application note from the great firm from USA

各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8(CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8 )

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

VHDL的源码100例，包括加法、减法、存储、触发等，是初学者、开发人员的必备手册-VHDL source code of the 100 cases, including the addition, subtraction, storage, trigger and so on, is for beginners, developers must Manual