maxplus2为开发环境 vhdl编写的自由 计数器 程序

LDPC QC-LDPC 基于FPGA的QC-LDPC实现 论文(LDPC QC-LDPC FPGA-based QC-LDPC detailed implementation steps Thesis)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).

自适应滤波，对输入信号进行选择性的加权处理，使输出达到最优化，并且能够跟踪和适应系统和环境的动态变化(Least mean square，of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)

维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA(viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA)

在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)

libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

用VHDL编写的JK触发器  用VHDL编写的JK触发器 用VHDL编写的JK触发器

说明：  qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)