VHDL

说明：  用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)

串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。(uart communication)

用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

自己写的扩展功能时钟，增加了年、月日计时，verilog代码，已在spatarn3实现。-Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.

说明：  运用VHDL描述函数发生器的各个波形，可有构成多功能函数发生器。(VHDL description of the use of various function generator waveforms, can constitute a multi-purpose function generator.)

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

TLC5615串行DA的驱动接口,采用verilog编程(TLC5615 driver DA serial interface using verilog programming)

8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......

dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)