VHDL

一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)

VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue

3 Digit BCD to 7 segment indicator decoder

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证-By the VHDL language using the D flip-flop is QUARTUES environment has been tested

假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

十分基础的CCD的测试程序，大家可以下载调试CCD(this is a ccd test chengxu ,it is very good to use ,you can down it )

VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)

数字频率计的设计，显示0~999的频率 整个程序代码都是通过vhdl语言来完善的 功能模块多样，详细的介绍了多模块的各个功能

基于fpga的液晶驱动开发过程相关资料，用于借鉴和学习-Fpga-based LCD driver development process relevant information, for reference and learning