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alu
说明: 用Verilog编写的简单的运算单元(ALU),可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)
- 2009-07-28 16:20:52下载
- 积分:1
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uartfifo
串口通信例程,使用FIFO数据缓存。Verilog源码,基于FPGA的uart开发,加深理解。(uart communication)
- 2017-04-20 22:16:21下载
- 积分:1
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用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制....
用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.
- 2022-12-17 02:20:02下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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Write their own extensions clock, an increase of the year, month day time, veril...
自己写的扩展功能时钟,增加了年、月日计时,verilog代码,已在spatarn3实现。-Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.
- 2023-01-04 22:35:04下载
- 积分:1
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VHDL
说明: 运用VHDL描述函数发生器的各个波形,可有构成多功能函数发生器。(VHDL description of the use of various function generator waveforms, can constitute a multi-purpose function generator.)
- 2009-08-18 16:54:24下载
- 积分:1
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全部通过,是我的精心设计,完全满足初学者的要求。
全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-02-20 15:52:11下载
- 积分:1
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tlc5615
TLC5615串行DA的驱动接口,采用verilog编程(TLC5615 driver DA serial interface using verilog programming)
- 2009-04-27 11:59:22下载
- 积分:1
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8位CPU软核设计与应用研究
8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......
- 2022-03-21 23:18:32下载
- 积分:1
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fpga_dsp_simple
dsp和fpag通信的测试程序,包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
- 2013-04-14 15:17:20下载
- 积分:1