用verilog编写的1024点的fft快速傅立叶变换

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

DE2 altera board vhdl design

自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)

its a Fifo BASED design i also Interface DAC2904

USB口的设计，包括驱动程序的设计，以及软件的安装演示，软件的介绍，以及工作模式-USB port design, including the driver design, and installation of software, presentation, software presentation, and working models

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库，创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化，免去繁杂的手动操作，是创建这个仿真库最简洁的方法之一-Annex compxlib introduce how to use Xilinx

8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for

cic设计 verilog verilog(cic verilog design verilog)

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)