三种方法编写多路选择器的VHDL源代码 分别使用if else ,select ,when 语句...

基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)

An odd parity checker as an FSM using VHDL

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过-This is a VHDL language used to describe auto-configuration of the I2C module, the use of the I2C from opencores.org nucleus, the cyclone in the altera-chip debugging through

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

此演示展示了如何利用两个 PmodRF1 无线无线电收发器进行数据通信。 该项目分为两个组成部分，一个基站和远程站。每个站是 由 Cerebot 纳米微控制器板，接收从温度数据控制 PmodTMP 温度计。 从监控站的温度数据通过无线方式传输到基站使用 两个 PmodRF1s。一旦基站接收到的远程温度数据，它显示两个 PmodCLS 显示屏上的基地和远程温度。远程站然后再睡 30 秒钟，以节省电池电量。30 秒后远程站花和传输另一种 温度读数和进程重复。

说明：  OFDM的简易verilog仿真程序，环境是quartus，版本需要7.2以上(OFDM Modulation and Demodulation using Verilog in Quartus)

LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board