三种方法编写多路选择器的VHDL源代码 分别使用if else ,select ,when 语句...

存储示波器，功能齐全通过验证，毕业设计用-Storage oscilloscope, a full-featured validated, graduation design

Viterberi 解码器使用 vhdl 编程实现将被用于制作增强功能

FFT implementation using C program

说明：  本文档对LTE进行了详细的介绍，是一本LTE入门的好书(This document is a detailed introduction to LTE, is a good book to get started with LTE)

This is the Spartan 3E tutorial_02.

8对于输入密码锁的键，假设重置后七个灯显示" 0"，并且使用sw1、sw2、sw3 3，只需按任意sw1、sw2、sw3，将使七个灯显示值相加" 1

自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)

Project manager is reak vhdl old man

说明：  实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.