一个双向总线的vhdl实现

介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进 制码转换成8421BCD 码的原理、设计思路和软件实现。-Introduction based on Altera

基于FIR滤波器的LMS自适应算法的FPGA实现,verilog语言(FIR filter based on LMS adaptive algorithm on FPGA, VHDL language)

基于状态机的优秀SPI输出程序（以DAC7512为基础，可修改）(VHDL code about SPI)

Synopsys 8051 IP core documentation.

简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform. Please configure it according to the test environment before download and implement the program to FPGA)

本文详细介绍了我们的电气工程项目；

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

说明：  实现了从摄像头读取数据到液晶的显示，利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)

DDS in our camera design

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)