HDLC some relevant documents, HDLC design may be very helpful!

Verilog OTP ROM source code

vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统

该程序用vhdl编写的vga显示的小游戏，到时屏幕上会显示一个小球，一根棒子，一面墙，棒子可以通过按键控制来移动。而小球在不停的运动，遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)

四选一编程语言，可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.

说明：  PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

SDR SDRAM 控制器的源代码 altera公司的(source code from altera)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for

vhdl random numbergenerater

可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)