ALU指令

艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)

布尔乘法器带testbench好用的工程啊(Boolean multiplier works with testbench nice ah)

程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

Simulating the functions of POC.(Simulating the functions of POC. In VHDL, with ISE.)

实现基于FPGA的vga显示，亲测能编译得过，不同开发版应该要相应改动（PS: 不太了解）

数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)

基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

滤波器 Generaic FIR Filter(Generaic FIR Filter)