detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system desi...

16位高速数字相关器的VERIOLOG程序，已经编译通过了，可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)

pngenerator的vhdl代码。我们可以在cdma的fpga实现中使用它；

每次开机都将次数加1 并存储到EEPROM。这样就能直观的看到机器的使用次数 用P1口 LED做为显示，次数大于256是将溢出，按复位模拟开机 或者直接通过开关开机(Each boot will add a number of times and stored to the EEPROM. So you can visually see the frequency of use of the machine as with P1 port LED display, the number is greater than 256 will overflow, analog power or press the reset switch power directly through)

FIR filter up to 128x

altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

Control with DAC conversion

VHDL语言教材-The teaching material of VHDL Language

交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证-Traffic lights controller VHDL design, can be controlled by traffic lights at the crossroads of the conversion, through the target chips EPF10KLC84-4 verification