Altera 基础篇公司书籍源码

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

Vga in vhdl using spartan 3e board basys

RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine

design through verilog hdl

说明：  verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE

Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display

zedboard原理图详细，PCB板焊接方便，每个接口表明清楚。(Zedboard schematic in detail, PCB board welding is convenient, each interface that clearly.)

数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能(Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when)