Altera 基础篇公司书籍源码

FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序！！(FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !)

说明：  ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

基于脉动结构的有限域乘法器，verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

液晶显示屏显示汉字“年”的驱动程序VHDL(nian VHDL)

说明：  基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

simple code of some kind of base decoder based on verilog

a sequence generator

that file is different I2S example

出租车模块设计加nios2设计cup程序代码 出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code