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percent
verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)
- 2005-03-08 21:33:38下载
- 积分:1
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electric-8.08
The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:
* Custom IC layout
* Schematic Capture (digital and analog)
* Textual Languages such as VHDL and Verilog
(The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:* Custom IC layout* Schematic Capture (digital and analog)* Textual Languages such as VHDL and Verilog)
- 2009-01-09 20:01:17下载
- 积分:1
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freq_100M
用于检测100MHZ频率,带51单片机软核,控制外部液晶显示器以及按键等(Used to detect 100MHZ frequency, with 51 SCM soft core, control of external LCD monitors and buttons, etc.)
- 2017-07-28 09:57:56下载
- 积分:1
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cnt10
用Quartus II开发的一个十进制计数器,包括仿真波形,下载文件,是完整工程。(With the Quartus II development of a decimal counter, including the simulation waveform, download files, is the complete project.)
- 2011-05-23 21:50:52下载
- 积分:1
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8051_VHDL
mc8051代码,里面功能齐全,调试方便(mc8051 code, inside a full-featured, easy debugging)
- 2008-03-28 14:54:19下载
- 积分:1
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verilogexample
verilog学习资料。附带简单的源代码列子,可以直接使用和仿真。(verilog learning materials. Source code with a simple Lie Zi, and simulation can be used directly.)
- 2011-05-26 11:53:24下载
- 积分:1
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AES-on-FPGA
AES算法在FPGA上的实现,对AES算法所用的器件资源进行了总结(AES on FPGA the Fastest to the Smallest)
- 2014-12-31 10:06:46下载
- 积分:1
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ADC实验
基于stm32开发平台的,模拟ad采样程序设计,可直接下载使用(stm32 zhijiexiazaishiyong)
- 2018-02-02 00:32:43下载
- 积分:1
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sdram-source
SDR SDRAM 控制器的源代码 altera公司的(source code from altera)
- 2010-06-09 19:35:03下载
- 积分:1
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Adder4
本设计是设计了一个4位全加器的内容,是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)
- 2009-05-11 19:50:58下载
- 积分:1