DMA_controller

基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)

uart代码dsdlab与我的时钟代码.it是一个用于实现uart设计的verilog代码代码。这个是数字系统设计实验室的实践。

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

r80515源代码，包含说明文档。FPGA验证通过(r80515 source code, including documentation. Verified by FPGA)

对delta sigma进行设计，实现delta sigma ADC的设计(this is use for delta sigma adc ,and design and achieve adc)

verlog通过FPGA实现数字钟，包含时间计数，秒表和闹钟等功能

采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)

根据计算机原理与设计进行设计，完整的单周期cpu，已经仿真完成

uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device