SPI实现IP，用verilog实现

Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix

CIC 补偿滤波器。采用两种方法来设计，一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

Link the VGA adapter located in the altera DE2board to a monitor

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

这个verilong代码实现的功能是radar processing的功能。(This verilong code function is radar processing functions.)

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)

verilog xilinx IP实现FFT仿真(Verilog xilinx IP implementation FFT simulation)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

使用ALTERA的FPGA控制SDRAM的verilog程序(Use ALTERA s FPGA to control SDRAM s verilog program)