SPI实现IP，用verilog实现

在FPGA上实现的图像处理中值算法，其中包含对输入数据的控制，内容详细，如果需要复杂的 图像滤波算法只需要修改中值模块即可。在altera上可用，如果要再xilinx上使用，只需要将fifo替换即可

对输入视频图像处理，在图像中叠加十字光标，光标颜色可以自动反色(The input video image processing, the image superimposed cross cursor, the cursor can be automatically color color)

An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.

在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

基于FPGA的DPSK调制，包括matlab仿真代码，NCO载波发生器，绝相变化，上变频等，基于Altera FPGA实现，并通过仿真验证。

说明：  VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

this project is about FIR FIlter By VHdl codes in the ISE.

利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)

Altera board Mp3 project