SPI实现IP，用verilog实现

FPGA，用VHDL语言产生可调的PWM波(FPGA, VHDL language adjustable PWM wave)

axi slave 模型，verilog描述，自己可以根据自己的设计适当修改。基本功能可能存在bug，不过是模型，大家可以自己稍作修改。

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)

rebuild file in check for

使用VHDL语言实现的一个自动售货机的程序。适合VHDL初学者使用。(VHDL language using a vending machine program. VHDL suitable for beginners.)

BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

说明：  该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)

SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)