SPI实现IP，用verilog实现

VHDL TESTBENCH书写规范，对学习FPGA的同学很有帮助，掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)

cvery high compatibles for quartus

无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)

电梯控制，包括楼层按键相应，显示上下状态。(Elevator control, including the floors of the corresponding button to show the whole state.)

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

《编写VHDL测试概述》的英文原版讲述了如何使用VHDL写测试凳程序("Writing VHDL test overview" of the English original to write about how to use VHDL test bench program)

奇数分频-此程序对输入频率sysclk有奇数（X）分频的功能(Odd frequency- this program has an odd number of input frequency sysclk (X) frequency function)

该项目利用NEXYS3（斯巴达6）董事会4显示器和它的编程verylog 启动白衣100 MHz的时钟和我们使用preescaler换下来的frecuency，非常有礼貌的观点

数字逻辑与系统的关于所有的器件74LS的介绍，功能表(Digital Logic and System devices 74LS on the introduction of all the menu)

design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)