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Verilog实现按键消抖，工程，已下板验证通过。(Verilog achieves keystroke jitter elimination. The project has been validated on the lower board.)

用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself.

这是一个用verilog硬件描述语言写的FPGA上的别踩白块儿游戏，工程建立在altera的quartus ii上，由液晶屏显示画面，小键盘操控，提供了一种比较好的编程思路，可以根据该程序的思想写出更多的游戏作品。

说明：  示波器设计，首先，AD模块对模拟信号进行采样，触发电路根据采样信号判断触发条件。满足触发条件后，连续采样一定数量的点（本系统中为640个点），存储到RAM中。峰峰值、频率计算模块对RAM中储存的波形数据进行计算，得到波形的频率以及峰峰值；VGA模块将波形显示出来，并显示计算得到的峰峰值和频率数值。(Firstly, the ad module samples the analog signal, and the trigger circuit judges the trigger condition according to the sampling signal. After meeting the trigger conditions, a certain number of points (640 points in this system) are sampled continuously and stored in RAM. The peak to peak and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak to peak of the waveform; the VGA module displays the waveform and displays the calculated peak to peak and frequency values.)

基于芯片5CSEBA6U2317，实现按键控制LED灯闪的速度的Verilog实现。(Realize the Verilog realization of the flow lamp.)

它是基于Verilog硬件描述语言浮动乘法器的数字化设计。该设计可以实现全功能，是更好的灵活性，其理论基础上浮动计算并补偿位移倍增。

APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)

在zedboard上运行的神经网络架构，方便移植。(Run lenet-5 on zedboard)