开源软核处理器OpenRisc的SOPC设计

基于FPGA的1024点流水线工作方式的FFT实现,适合fpga的技术人员做信号处理参考-FPGA based on the work of the 1024-point pipelined FFT approach the realization of the technical staff for doing fpga signal processing reference

在实现 OFDM 中，必须有筛选器，以提高无线电信号的质量。一般情况下，筛选器应用于 OFDM 的类型是 FIR 滤波器。FIR 滤波器是方便使用，因为线性相位的未来。所以，我研究它与实现 FIR 滤波器 VHDL 语言一轮。这段代码是完全测试。但我是节约资源的 FPGA 改进范围。

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

这是一些小代码的集合 希望能对大家有所帮助(This is a collection of some small code for all of us hope to be helpful)

fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand

AES算法部分模块行位移列变换以及主题程序加密解密(AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program)

内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code

VHDL编程语言设计，显示灯，显示VHDL字样。-VHDL programming language design, indicator lights, indicating the word VHDL.

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)