通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用...

System Generator

this file is vhdl code of alu

Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see

spwm dcac逆变 fpga与单片机一起作用(sdad)

最新的CCSDS高光谱图像压缩算法标准的FPGA实现，用VHDL实现的。可参考。绝对物有所值，希望对你的设计有所帮助!

01 线性调频信号的卷积功能测试（匹配） 02 LFM一维距离像 03 MATLAB联合FPGA仿真输入/输出功能测试 04 解速度模糊 05 扩展目标检测(01 LFM Test function of "conv" 02 LFM Range 03 MATLAB and FPGA 04 resovle speed resolution 05 Extended moving target)

DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method

xilinx的zed板详细开发资料，对初学者和开发人员都有帮助(The Xilinx zed board detailed development information, helpful for beginners and developers)

本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation