登录
首页 » VHDL » 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算...

树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算...

于 2022-09-04 发布 文件大小:636.00 B
0 106
下载积分: 2 下载次数: 1

代码说明:

树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • This is the FPGA, a simple routine, LED keyboard display program, very time we s...
    这是FPGA的一个简单例程,LED键盘显示程序,非常时候大家入门学习-This is the FPGA, a simple routine, LED keyboard display program, very time we started to learn
    2022-06-18 21:18:24下载
    积分:1
  • Arbitrary odd
    任意奇数分频,只要修改N即可实现 可验证-Arbitrary odd-numbered sub-frequency, as long as the modified N can realize verifiable
    2022-03-19 01:50:16下载
    积分:1
  • VerilogDHL
    VerilogHDL教程,很详细全面的Verilog教程,循序渐进,由浅入深,十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)
    2011-07-13 14:19:53下载
    积分:1
  • 1553B的编解码程序是有用的给大家分享分享
    1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
    2022-07-28 09:59:52下载
    积分:1
  • forug_2016.03
    说明:  formality2016 userguide
    2019-10-29 14:59:40下载
    积分:1
  • fpga实例程序代码
    关于FPGA的一些例程,包括CORDIC数字计算机的设计,RS(204,188)译码器的设计等。(Some routines on FPGA include the design of CORDIC digital computers, the design of RS (204188) decoders, etc.)
    2018-07-21 19:08:25下载
    积分:1
  • 本实施multilplier在vhdl.this源代码是有用的电脑学习…
    this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
    2022-01-31 00:27:28下载
    积分:1
  • matlab2DPSK
    蒙特卡洛仿真图 这个程序对2psk信号进行仿真 前提是把信号能量归一化了 (This programme intend to realize the simulation of 2DPSK through MonteCarlo experiment. intends )
    2013-05-04 13:18:00下载
    积分:1
  • xapp1071
    高速ADC及DAC接口的参考设计。在Xilinx FPGA上实现。(Reference design of xapp1071.)
    2012-05-22 15:34:04下载
    积分:1
  • gtwizard_254_127_ex_1113_3
    配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
    2019-06-17 21:33:56下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载