树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算...

vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统

说明：  uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx

---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

代码来源http://www.spacewire.co.uk/video.html，需要CRT显示ITU.656格式的视频的可以参考

大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51

描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)