BMD_PCIE

  自己根据xapp1052修改的源代码，已经编译成功，并应用在开发板上。(According xapp1052 own modified source code has been successfully compiled and used in the development board.)

BMD_PCIE
........\bit
........\cdc
........\...\1.cpj,110923,2015-10-03
........\...\trn_mon.cdc,23546,2015-10-03
........\ip
........\..\bmd_design
........\..\..........\doc
........\..\..........\...\s6_pcie_ds718.pdf,174278,2015-10-03
........\..\..........\...\s6_pcie_ug654.pdf,52979,2015-10-03
........\..\..........\example_design
........\..\..........\..............\pcie_app_s6.v,7674,2015-10-03
........\..\..........\..............\PIO.v,5551,2015-10-03
........\..\..........\..............\PIO_32_RX_ENGINE.v,18903,2015-10-03
........\..\..........\..............\PIO_32_TX_ENGINE.v,12292,2015-10-03
........\..\..........\..............\PIO_EP.v,7893,2015-10-03
........\..\..........\..............\PIO_EP_MEM.v,13276,2015-10-03
........\..\..........\..............\PIO_EP_MEM_ACCESS.v,10884,2015-10-03
........\..\..........\..............\PIO_TO_CTRL.v,3635,2015-10-03
........\..\..........\..............\xilinx_pcie_1_1_ep_s6.v,18055,2015-10-03
........\..\..........\..............\xilinx_pcie_1_lane_ep_xc6slx45t-fgg484-2.ucf,6183,2015-10-03
........\..\..........\implement
........\..\..........\.........\implement.bat,1111,2015-10-03
........\..\..........\.........\implement.sh,965,2015-10-03
........\..\..........\.........\xst.prj,712,2015-10-03
........\..\..........\.........\xst.scr,137,2015-10-03
........\..\..........\s6_pcie_readme.txt,6088,2015-10-03
........\..\..........\simulation
........\..\..........\..........\dsport
........\..\..........\..........\......\gtx_drp_chanalign_fix_3752_v6.v,6817,2015-10-03
........\..\..........\..........\......\gtx_rx_valid_filter_v6.v,11752,2015-10-03
........\..\..........\..........\......\gtx_tx_sync_rate_v6.v,13971,2015-10-03
........\..\..........\..........\......\gtx_wrapper_v6.v,26730,2015-10-03
........\..\..........\..........\......\pcie_2_0_rport_v6.v,54027,2015-10-03
........\..\..........\..........\......\pcie_2_0_v6_rp.v,81864,2015-10-03
........\..\..........\..........\......\pcie_brams_v6.v,8352,2015-10-03
........\..\..........\..........\......\pcie_bram_top_v6.v,5981,2015-10-03
........\..\..........\..........\......\pcie_bram_v6.v,11345,2015-10-03
........\..\..........\..........\......\pcie_clocking_v6.v,11559,2015-10-03
........\..\..........\..........\......\pcie_gtx_v6.v,24144,2015-10-03
........\..\..........\..........\......\pcie_pipe_lane_v6.v,12687,2015-10-03
........\..\..........\..........\......\pcie_pipe_misc_v6.v,7651,2015-10-03
........\..\..........\..........\......\pcie_pipe_v6.v,36163,2015-10-03
........\..\..........\..........\......\pcie_reset_delay_v6.v,4011,2015-10-03
........\..\..........\..........\......\pcie_upconfig_fix_3451_v6.v,5595,2015-10-03
........\..\..........\..........\......\pci_exp_usrapp_cfg.v,6844,2015-10-03
........\..\..........\..........\......\pci_exp_usrapp_com.v,74552,2015-10-03
........\..\..........\..........\......\pci_exp_usrapp_pl.v,4271,2015-10-03
........\..\..........\..........\......\pci_exp_usrapp_rx.v,8600,2015-10-03
........\..\..........\..........\......\pci_exp_usrapp_tx.v,105840,2015-10-03
........\..\..........\..........\......\xilinx_pcie_2_0_rport_v6.v,18688,2015-10-03
........\..\..........\..........\functional
........\..\..........\..........\..........\board.f,1284,2015-10-03
........\..\..........\..........\..........\board.v,5755,2015-10-03
........\..\..........\..........\..........\isim_cmd.tcl,17,2015-10-03
........\..\..........\..........\..........\simulate_isim.bat,674,2015-10-03
........\..\..........\..........\..........\simulate_isim.sh,643,2015-10-03
........\..\..........\..........\..........\simulate_mti.do,268,2015-10-03
........\..\..........\..........\..........\simulate_ncsim.sh,780,2015-10-03
........\..\..........\..........\..........\simulate_vcs.sh,1022,2015-10-03
........\..\..........\..........\..........\sys_clk_gen.v,2928,2015-10-03
........\..\..........\..........\..........\sys_clk_gen_ds.v,3067,2015-10-03
........\..\..........\..........\..........\wave.do,2134,2015-10-03
........\..\..........\..........\..........\wave.sv,2922,2015-10-03
........\..\..........\..........\..........\wave.tcl,1443,2015-10-03
........\..\..........\..........\..........\wave.wcfg,9939,2015-10-03
........\..\..........\..........\tests
........\..\..........\..........\.....\tests.v,18647,2015-10-03
........\..\..........\source
........\..\..........\......\bmd_design.v,52685,2015-10-03
........\..\..........\......\gtpa1_dual_wrapper.v,16439,2015-10-03
........\..\..........\......\gtpa1_dual_wrapper_tile.v,38494,2015-10-03
........\..\..........\......\pcie_brams_s6.v,8185,2015-10-03
........\..\..........\......\pcie_bram_s6.v,6099,2015-10-03
........\..\..........\......\pcie_bram_top_s6.v,5681,2015-10-03
........\..\bmd_design.gise,1171,2015-10-03
........\..\bmd_design.ncf,0,2015-10-03
........\..\bmd_design.veo,7345,2015-10-03
........\..\bmd_design.xco,4154,2015-10-03
........\..\bmd_design.xise,7028,2015-10-03
........\..\bmd_design_flist.txt,2901,2015-10-03
........\..\bmd_design_verilog_example_project.xise,14966,2015-10-03
........\..\bmd_design_xmdf.tcl,13211,2015-10-03
........\..\coregen.cgp,240,2015-10-03
........\..\gen_bmd_design.tcl,1140,2015-10-03
........\..\tmp
........\..\...\_cg
........\..\...\_xmsgs
........\..\...\......\pn_parser.xmsgs,786,2015-10-03
........\..\_xmsgs
........\..\......\cg.xmsgs,1373,2015-10-03
........\..\......\pn_parser.xmsgs,1817,2015-10-03
........\mcs
........\...\bmd_pcie.cfi,455,2015-10-03
........\...\bmd_pcie.mcs,4083265,2015-10-03
........\...\bmd_pcie.prm,672,2015-10-03
........\par
........\...\BMD_PCIE
........\...\........\BMD_PCIE.xise,44927,2015-10-03
........\...\........\iseconfig