Program to implement convolution through VHDL

VHDL实用教程，详细介绍VHDL语法、开发环境、应用实例等。。。(VHDL course)

FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

fft 1024点verilog代码,适用于基-4的FFT算法描述，使用quartus，modelsim，(fftpoint 1024 verilog code)

频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT

8位有符号编码的整数基改性

xilinx 的8B10B编解码源码, 里面有仿真模型,用以测试验证(xilinx 8B10B encode/decode source)

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

说明：  ZYNQ中 PS 端 CAN接口的基本使用方法，并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)

i2s串行线广泛用于音频通信中,这里包括了master和slave的代码.-i2s serial lines widely used in audio communication, here including the master and slave codes.

MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)