实现两路数字信号的鉴相功能，最后通过静态LED显示出来，该程序通过硬件的测试...

这一计划表明它是如何在如此逻辑门是门NAND，什么它NAND它是结合两个闸门之一，并没有。

W elcome to X CELL, the new Xilinx customer newsletter. By sending us your development system registration card you automatically became n charter subscriber to this quarterly publication. It is our intent to make this an informative, easy to read, responsive and-hopefully- interactive newsletter. We want to supply you with early and correct information, tell you about the status of our products and about our plans, about bugs and their workarounds, give you applications ideas and convey to you some of the en thusiasm that we feel for our Programmable Gate Arrays. If you have questions or suggestions, please send them to me. II Letters to the Editor make a newsletter more lively. Peter Alfke, Editor

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

利用Verilog语言中的函数调用实现阶乘运算的功能(Function calls use Verilog language implementation of the factorial function computing)

COUNTER 用于xilinx硬件，里面已建工程，修改ucf即可。设计由3部分组成，计数器，100M分配时钟，顶层模块，其中顶层模块包括计数器和分频器。

基于fpga的实时视频采集与显示 高速化 小型化-fpga

altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.

一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)

大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51

uart通信的Verilog实现,包含rx tx 以及testbench(Verilog implemention of UART telecommunicate)