计数器，vhdl，调试通过。

基于DS1302芯片的VERILOG 语言数字钟。可实现年月日时分秒显示。(DS1302 chip-based language VERILOG digital clock. Date can be achieved when every minute display.)

卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。(Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.)

512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII

数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

ofdm的verilog程序 利用ＦＰＧＡ实现-OFDM FPGA using the Verilog procedures realize

合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection

基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)

ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven

应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)