计数器，vhdl，调试通过。

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

n_bit_paralleLoadShiftRegJK

封装PS2接口驱动，用verilog编写！适用于键盘，鼠标等PS2接口的器件。(failed to translate)

非常好的SDRAM Controller 设计文档。工程必备-SDRAM Controller Design of a very good document. Works required

在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码-In Altera

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)

本练习的目的是检查加法、减法和乘法运算电路。每个

用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)