基于BASYS开发板的波形发生器和示波器设计

说明：  Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers

基于 CPU 的精确计时器，时钟频率越高，计时越准(Based on the exact CPU timer, the higher clock frequency, the more time-quasi-)

ldpc译码算法介绍及fpga verilog系统方案设计，包括log_bp算法、min_sum算法、scaling_min_sum算法等(introducing the ldpc code decoding algorithm and the related system design，including the log_bp,the min_sum and the scaling_min_sum)

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `

This code that genetes a square, sawtooth and a triangular waveform. It is useful for designing a function generator in VHDL.

8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

verilog code,about oc8051

华为FPGA设计全套资料，学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)