uart vhdl代码

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)

说明：  一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

7对于进入密码锁的按键，假设复位后七个灯显示" 0"，而使用sw5、sw6 2，则只要按下并松开sw5后七个灯就显示" 5"，而只要按下并松开sw6，七个灯就正确显示值" 6

cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)

说明：  Implementation of CORDIC atan block in VHDL

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)

说明：  可调矩阵，最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

Ethernet MAC-MII interface of Transmit