伪随机二进制序列无符号17位计数器

VerilogHDL课件，老师现在正拿这个上课-VerilogHDL courseware, teachers are now using this class

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

FSM_test for textbanch in vhdl-FSM_test

vhdl code for carry lookahead addder

使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)

APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)

ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller

该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)

基于DB8小波变换的verilog代码设计，支持Avalon总线(Verilog DB8 Wavelet Transform Based on code design, support Avalon bus)

spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)