ad7667.hdl

非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful

微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)

说明：  VC707_MIG_DDR3.sim文件夹中是仿真的文件：testbench和DDR3模型参数 VC707_MIG_DDR3.srcs文件夹中是源文件，包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)

The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.

ARM教程,理解精辟，言简意赅，不错哦，欢迎大家看看(arm language )

有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

HDL example source code 1/5 tff_a

BUS documentation and map reffereces

采用VHDL编写的频率计，模块划分清晰易懂，基本原理为检测一个闸门脉冲周期内的信号次数，采用四段数码管显示