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xilinx平台DDR3设计教程之仿真篇_中文版教程
DRD3在Xlinix平台上的设计教程以及仿真(DRD3 design tutorial and Simulation on Xlinix platform)
- 2018-11-02 11:18:06下载
- 积分:1
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SASX
Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
- 2020-06-24 11:40:02下载
- 积分:1
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Microsoft-Word--(11)
信号源模块源程序,可以实现程序模块的实现,然后发生需要的程序(Source module source code, you can achieve the realization of the program modules, and the occurrence of the required procedures)
- 2014-12-30 11:12:32下载
- 积分:1
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Lab5.5_Led_FPGA
使用verilog在fpga开发板实现流水灯,包括整个工程文件(This code is used for early learners to study verilog。)
- 2014-05-07 19:57:24下载
- 积分:1
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VHDL版的C51核(MC8051)
VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)
- 2022-06-19 21:32:45下载
- 积分:1
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FPGA-DSP
vhdl编写的FPGA与DSP接口程序,在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)
- 2021-01-08 10:58:51下载
- 积分:1
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32位/33M 从模式(target)PCI接口参考设计,Lattice提供。由于PCI时序较复杂,此设计仅能供参考...
32位/33M 从模式(target)PCI接口参考设计,Lattice提供。由于PCI时序较复杂,此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
- 2023-09-04 17:30:04下载
- 积分:1
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design a module from a trip data flow channeling Lane detected bitstream "1...
设计一个模块,从一个窜行数据流里检测出码流“11100”,这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
- 2022-07-06 13:42:26下载
- 积分:1
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用vhdl描写的通用异步改进dram控制器,经过编译器综合和仿真测试,符合设计要求。...
用vhdl描写的通用异步改进dram控制器,经过编译器综合和仿真测试,符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- 2022-04-19 09:59:57下载
- 积分:1
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VHDLrefencebook
doulos公司出的VHDL学习工具,非常易学易懂!~(doulos company out of the VHDL learning tool, very easy to understand! ~)
- 2016-10-09 15:45:57下载
- 积分:1