Oregano Systems 8051 ip core

基于FPGA的误码测试仪 （已注释） --锁相环-M序列生成模块--数据接口模块- --模拟信道模块---本地M序列生成模块--同步模块--误码统计模块--显示模块-(FPGA-based BER tester)

使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)

vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)

vhdl golden reference guide

此代码能够使得键盘控制液晶，实时的进行书写，按下Backspace清屏(This code enables the keyboard to control the LCD, in real-time writing, press Backspace clear the screen)

Fonts for LCD 162x64 (6x8)

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

i have coding for verilogHDL and VHDL. so please i want know that coding..

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

ＵＣ1698Ｕ驱动160*160ＬＣＤ中文应用及例程(UC1698U driver 160* 160LCD Chinese applications and routines)