Oregano Systems 8051 ip core

VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动-VGA display interface Verilog control procedures. Control for VGA display driver

Pipeline processor verilog components

verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga

通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.

应用背景这是lm016液晶的VHDL代码。lm016液晶显示器基本上由2行和2列组成。有2种类型接口，8）1位接口2）4位接口在这个包中给出了8位接口代码因为它很容易，但唯一的缺点是，它使用了更多的引脚数据和指令传输。关键技术此代码是 测试；FPGA开发板–xc6slx9-tqg144斯巴达6注意：液晶显示器引脚数字引脚47液晶使能引脚数字引脚50LCD RW引脚数字引脚48LCD D0引脚数字引脚51液晶D1引脚数字引脚55LCD D2引脚数字引脚56LCD D3引脚数字引脚57LCD D4引脚数字引脚58LCD D5引脚数字引脚59LCD D6引脚数字引脚61液晶D7引脚数字引脚62

本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.

嵌入式应用开发技术白金手册源代码 嵌入式应用开发技术白金手源代码-this is a vhdf code

一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文(master and doctor dissertation)

设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report

基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal