altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TEST...

使用并行结构对32位数据进行前导零检测，使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)

SOC Verfication Methodology and Techniques

这是“VHDL设计”讲稿，希望对初学者有用，-"VHDL design" script, useful for beginners, thank you! !

自己收集的VHDL例程代码，适合初学者学习用，希望能给大家带来帮助。-Collected their own routines VHDL code, suitable for beginners to learn, I hope we can help.

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

FPGA设计软件的绝佳入门书籍，本人珍藏，全部吐血奉献之2，请大家赶紧下！-FPGA design software, an excellent entry-books, I treasure all the blood sacrifice of 2, please hurry under the U.S.!

杨小牛大神的软件无线电，做信道化或者宽带数字接收机的可以下载(Software Radio written by XiaoNiu Yang,people who deal with channelization or wideband digital receiver can download)

12232型号LCD液晶屏显示程序，简单易懂(12232 Model LCD screen display program, easy to understand)

实现拟想要的音乐，基于at89s51单片机的电子琴设计！(To achieve the desired music to be based at89s51 keyboard microcontroller design!)

这一计划表明它是如何在如此逻辑门是门NAND，什么它NAND它是结合两个闸门之一，并没有。