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frequency-agility
本程序为捷变频信号的verilog源代码设计实现的仿真,并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)
- 2015-10-15 10:37:54下载
- 积分:1
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1024point-fft--using-verilog-hdl
1024点快速傅里叶变换,使用verilog hdl硬件描述语言(1024point FFT,using verilog hdl)
- 2013-03-09 10:54:42下载
- 积分:1
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41_eth_ddr3_lcd
说明: “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片,并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限,只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)
- 2021-03-21 00:33:00下载
- 积分:1
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Vhdl实现计算exp功能 在apex20k上经过验证
Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k
- 2022-07-21 03:19:31下载
- 积分:1
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占空比1:1的通用分频模块
占空比1:1的通用分频模块-1:1 generic-frequency module
- 2022-11-11 08:45:03下载
- 积分:1
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uart串行口,用Verilog编写的.供大家参考
uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
- 2022-07-17 22:14:09下载
- 积分:1
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interpolate4
调制信号后4倍内插的verilog代码,用于基带成型滤波器输入数据(4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data)
- 2017-04-20 15:52:09下载
- 积分:1
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简易数字信号分析仪(眼图)
采用VHDL语言编写,此题为全国大学生电子设计竞赛题目,产生一个伪随机信号,并用时钟提取模块提取时钟,最终能在示波器上获得眼图,验证实验结果。此程序已经经过本人亲自验证,完全可用,可用于电赛培训之中。
- 2022-07-22 14:59:00下载
- 积分:1
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adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分:1
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NIOSII-Qsys_v1.3.1
黑金刚FPGA开发板使用说明文档,讲诉了NIOS和Qsys的详细开发步奏,值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)
- 2015-03-25 13:42:03下载
- 积分:1