File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...

说明：  VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。(VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.)

在ISE12.4与TMS320F2812的XINTF接口，实现数据收发(In ISE12.4 TMS320F2812 the XINTF, data transceiver)

  该代码主要是针对TCD1500c 的时序图，用verilog 语言实现的TCD1500c的时序图，利用modelsim 进行仿真，并且通过测试。

详细设计了异步fifo格雷码中地址码的生效和Man标志的出现

FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization FPGA)

verilog vga 图像处理(verilog vga)

4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码-four electronic password lock with a keyboard scan button shake, LCD driver encryption

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

TCD1209D驱动程序 Verilog语言(TCD1209D driver Verilog language)