本例为DAC0832接口电路VHDL原代码

正弦信号发生器（可扫频）通过验证 正弦信号发生器-Sinusoidal signal generator (which can be swept) through the validation of sinusoidal signal generator

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

说明：  Matlab to hdl code for Least_square testbench

8051core-Verilog FPGA的51单片机内核源代码! -8051core-Verilog FPGA 51 Singlechip kernel source code!

Fixed-point base-2 logarithm (DW_log2) // Computes the base-2 logarithm of a fixed point value in the // range [1,2).

vhdl code for carry lookahead addder

并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

fpga测温的框图和源码 希望能帮到大家 没有测试 紧供参考-fpga vhdl

说明：  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)

六个数码码动态扫描接口程序，用VERILOG语言编写的-Six digital code dynamic scan interface program, using Verilog language