本例为DAC0832接口电路VHDL原代码

十一和通过vivado实现多周期cpu，各种作业再里面包含了(Realizing multi period CPU)

温度液晶显示演示程序 LCD数据线：P0口 LCD控制线：RS P20 RW P21 E P22 BUSY P07 18B20端口DQ ：P27 (Temperature of liquid crystal display demo Data line: P0 LCD LCD RS P20 RW P21 control line: E P22 BUSY P07 18B20 DQ : P27 port )

通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

色彩空间转换硬件实现，用于图像处理，编码，解码部分-Color space conversion hardware for image processing, encoding, decoding part of the

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

PS2 Module for Altera DE2

FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in

说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

xapp from xilinx very hard to find and very usefull application note from the great firm from USA

pngenerator的vhdl代码。我们可以在cdma的fpga实现中使用它；