本例为DAC0832接口电路VHDL原代码

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)

自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)

说明：  使用FPGA实现中值滤波算法，能够使数据直接使用该系统对数据进行中值滤波。(FPGA is used to realize the median filtering algorithm, which can make the data directly use the system for median filtering.)

BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示 -BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display

设计一个具有同步置1，异步清零的D触发器。 设计一个类似74LS160的计数器(Design an D trigger with synchronous reset 1 and asynchronous reset. Design a counter like 74LS160.)

数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)

基于VHDL的抢答器程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-Answer Based on the VHDL program, including complete source code, locking pin, as well as download files documents can be directly downloaded using

基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2

基于VHDL语言的循环码编码器的程序，以一个（15，6）循环码为例-VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example