The use of Altera' s FPGA

内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM

采用VHDL语言设计的基于LUT的正弦波发生器，已通过调试，并给出了pics仿真结果

Verilog code for RS-(255,239) encoder.

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.

针对AD9826驱动设计的Verilog代码，主要是配置ccd采样的设计(The Verilog code is designed for AD9826, to configuration ccd sampling )

at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)

说明：  100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的(100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation)

初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information

这是用Verilog写的RS485通信程序，可以使用，希望大家能够互相交流，(This is a Verilog writing RS485 communication program, can be used, I hope we can communicate with each other,)