Xilinx 的DDR SDRAM控制器，用Verilog HDL描述

适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.

随机数发生器

状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)

hdb3 using language VHDL(Indoor using VHDL language)

AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design )

VHDL子程序集,包括各种例程资料以及源码.-VHDL subprogram, including a variety of routine information as well as the source.

一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl

offset_cancellation code for matlab to hdl

本实验教程选用Xilinx公司的产品X9572，与之配套的开发软件为ISE4.1i，可进行原理图的输入和VHDL硬件描述语言的输入，并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.