本实验教程选用Xilinx公司的产品X9572，与之配套的开发软件为ISE4.1i，可进行原理图的输入和VHDL硬件描述语言的输入，并且可利用Modelsim进

说明：  All AMBA bus protocols - AXI3, AXI4, AXI4-Lite, ACE, AHB

Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog

基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)

Verilog经典教程，很好的学习Verilog的书籍，对学习硬件编程很有帮助。(Verilog classic handbook, good learning Verilog books, to learn hardware programming helpful.)

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation

基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机(FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game)

verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))

xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)