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5分代码及说明，verilog代码，几乎所有的IC面试都会问到这个问题，所以总结了一下发了上来，共同学习！-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!

讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。 注：原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)

去抖动状态机,外部按键转换状态,同时可去抖动-To shake state machine, the external key conversion state, while to the jitter

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

spartan 3 hardware reference document xilinx

基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)

全加器的VHDL程序实现及仿真-full adder VHDL simulation program and

moving tracking based in D5M camera tracking camera

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design