4X4keypad shake the module, the keys for false detection

基于fpga的uart串口通信协议，64位数据(Uart communication protocol based on fpga, 64-bit data)

32位二进制除法器2

圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)

基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码(Cpri interface based on verilog code, support various rate free switch, production products the actual application code)

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

vhdl 键盘程序，对键盘输入的字符进行判断，写入fpga中-VHDL key

vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)

VHDL Language Reference courses part4

沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)

篮球24s计时。计时器递减计数到零时，数码显示器显示‘0’并停止，同时发出报警信号(basketball 24 seconds)