4X4keypad shake the module, the keys for false detection

本文件是作为超大规模集成电路设计实验室课程（EC354）一部分进行的为期一学期的项目报告。我们的项目是一个4位8点FFT（快速傅立叶变换）核心的完全定制设计。实现的FFT类型是DIF（时间抽取）FFT。

这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning

实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 (Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)

a program which divides the clock by 3

Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件-Such as precision digital frequency of a project- including VHDL source code and compile the relevant documents after

fpga hardware hevc implementation

非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful

adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

说明：  用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)