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multiply_8_VHDL
由8 位加法器构成的以时序方式设计的8 位乘法器,采用逐项移位相加的方
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件,运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)
- 2014-04-11 16:58:04下载
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一篇比较好的spi接口的vhdl实现的参考
一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
- 2023-05-08 20:50:03下载
- 积分:1
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FPGA向SRAM中写入数据,VHDL编程
FPGA向SRAM中写入数据,VHDL编程-FPGA to the SRAM write data, VHDL programming
- 2023-05-04 17:45:03下载
- 积分:1
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FSK
频移键控FSK的Verilog实现,带测试文件,并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
- 2020-09-03 11:28:07下载
- 积分:1
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5.7
设计一个简单的FIR滤波器,并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)
- 2015-04-17 18:26:49下载
- 积分:1
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dac
说明: DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog(DA-chip SPI protocol output control does not read write-only FPGA with verilog)
- 2011-03-16 19:04:33下载
- 积分:1
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ug_dsp_builder
本文是Altera公司编写的dspbuilder的设计方法,但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)
- 2008-12-14 01:33:58下载
- 积分:1
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lut_multiplier
使用verliog设计实现LUT查找表乘法器,通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)
- 2021-04-09 10:18:59下载
- 积分:1
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eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1
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6
说明: 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口;如果要输出四位十进制数,就需要32的输出端口,这将占用大量的端口资源。采用串行扫描显示,我们只需要8+4共12个端口即可。其原理是:用一个四位的输出端控制,某一时刻只选中其中的一个LED(输出为‘1’表示选中),八位的输出端将该LED所需要显示的值输出;然后四位的输出端值改变,选中下一个LED。这样依次类推。如果选择的频率很快,达到50Hz以上,由于人眼的视觉暂留效应,看起来就像4个LED同时显示。
设计一个程序,输入四个一位十进制数,用4个LED显示出来。CLK采用频率可调信号发生器,逐渐改变频率,观察扫描频率的改变对输出效果的影响。
输入:连续脉冲,逻辑开关;输出:七段LED。
(4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously.
Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output.
Input: Continuous pulse, logic switches output: seven-segment LED.)
- 2010-06-21 22:07:59下载
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