VHDL语言串口接收数据

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

说明：  本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

Traffice LED Controller base on FSM 1. for crossroad, each road with 3 led: green, red, yellow. 2. only use one counter.

fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS

vhdl的很多例子，包括LED、lcd、按键、数码管等等，非常的实用。-VHDL of many examples, including the LED, lcd, keypad, digital control and so on, very practical.

说明：  在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation

VHDL book for reference

利 用 来 vhdl 设 计 p cm的 实 现-Vhdl design used for the realization of p cm

FFT的VHDL源代码-fft vhdl source code