VHDL语言串口接收数据

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)

8级cordic 算法verilog (8 cordic algorithm verilog)

Implementarea unui comparator pe 1 bit

基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

USB3.0开发板资料，采用CYUSB3.0(USB3.0 development board, using CYUSB3.0)

这是一个数字逻辑课程的电子表的实现，利用VHDL语言实现，初学者可以完全掌握，很有帮助。(This is the realization of the electronic timepiece a digital logic course, the use of VHDL language, beginners can fully grasp and helpful.)

简单的8个CPU，包含PDF文件。他们可以查看详细信息

说明：  verilog讲义 卡内基梅陇大学verilog课程讲义-unlocked 卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)