82 VHDL, verilog test case, involving a variety of grammatical rules. which is...

说明：  16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)

基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

4X4keypad的防抖动模块，用于假按键的检测-4X4keypad shake the module, the keys for false detection

fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver

riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.

蓝牙HCI―UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design

利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)