Quartus II

FPGA YCbCr444转YCbCr422实验 很好的参考(FPGA EP4CE40F23C6 YCbCr444 turn YCbCr422 experiment)

timblogiw.c timberdale FPGA LogiWin Video In driver.

主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly

应用VHDL语言编写交通灯的控制程序。 熟悉该语言的基本用法。-Application of VHDL language of the control procedures of traffic lights. Familiar with the basic use of the language.

To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.

本例为TLC7524接口电路VHDL原程序-Example for the TLC7524 interface circuit VHDL original procedure

数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)

TCD1209D驱动程序 Verilog语言(TCD1209D driver Verilog language)

在zedboard上运行的神经网络架构，方便移植。(Run lenet-5 on zedboard)

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)