Quartus II

Programmable Logic Design Quick Start Guide from Xilin Co.

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

说明：  Giao tiep Univesan ...

Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现-Hynix" s 8M Byte SDR SDRAM Simulation of the Verilog language

半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！-fen pin qi

vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示-vga programming. Realization of the three-mode vga control, generate horizontal color of the color of the shaft, and the chess grid color of the show

偶数分频，包括验证程序，verilog实现，可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated

this project is about FIR FIlter By VHdl codes in the ISE.

VHDL数字电路设计教程 乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)