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用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的-Using Verilog language organ procedures. GW48 teaching experiment with simulation boxes

FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages

使用Verilog编写的正弦波生成工程，使用ROM核产生，利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

产生长度为100的随机二进制序列 发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱 相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特） 接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特） 采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特） DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特） DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特） (Produce random binary sequence of length 100 The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits) The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits) DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits) DPSK and delay)

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 (Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)

vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)