基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行

关于基数分频技巧设计,基于VHDL语言,对实际设计有帮助-DIVIDE

在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)

一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理(A simple realization of a vending machine with verilog state machine design, there are design principles introduced word)

不足20元的PCI设计，含ABEL源代码。-PCI design less than 20Yuan ,including ABEL code

TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!

Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download

VHDL实现交通灯-VHDL traffic lights

说明：  浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准(floating_piont addition)

快速付里叶变换子程序所需 RAM 空间以输入的首地址为基址,向增加的方向扩展(Fast Fourier Transform subroutine RAM space required to input the first address of the site was to increase the direction of expansion)

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)