基于FPGA的电子密码锁的设计，内有Verilog HDL源码和各仿真图像

基于VHDL+FPGA的神经网络设计，实现简单的字符识别(Design of Neural Network Based on VHDL+FPGA to Realize Simple Character Recognition)

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested

说明：  实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

说明：  很好的免费学些 verilog教程 欢迎下载(Learn a good free download verilog tutorials welcome)

高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format

原理图输入法制作的32位加法器。。。。。。。。(adder32)

能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver(LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver)

硬件描述语言,verilog HDL,实现了解码器的设计-hardware description language, verilog HDL, the decoding of Design